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? semiconductor components industries, llc, 2011 february, 2011 ? rev. 9 1 publication order number: cat5419/d cat5419 dual digitally program- mable potentiometers (dpp ) with 64 taps and 2-wire interface description the cat5419 is two digitally programmable potentiometers (dpp ) integrated with control logic and 16 bytes of nvram memory. a separate 6 ? bit control register (wcr) independently controls the wiper tap position for each dpp. associated with each wiper control register are four 6 ? bit non ? volatile memory data registers (dr) used for storing up to four wiper settings. writing to the wiper control register or any of the non ? volatile data registers is via a 2 ? wire serial bus (i 2 c ? like). on power ? up, the contents of the first data register (dr0) for each of the two potentiometers is automatically loaded into its respective wiper control registers (wcr). the write protection (wp ) pin protects against inadvertent programming of the data register. the cat5419 can be used as a potentiometer or as a two terminal, variable resistor. it is intended for circuit level or system level adjustments in a wide variety of applications. features ? two linear ? taper digital potentiometers ? 64 resistor taps per potentiometer ? end to end resistance 2.5 k , 10 k , 50 k or 100 k ? potentiometer control and memory access via 2 ? wire interface (i 2 c like) ? low wiper resistance, typically 80 ? four non ? volatile wiper settings for each potentiometer ? recall of wiper settings at power up ? 2.5 to 6.0 volt operation ? standby current less than 1 a ? 1,000,000 nonvolatile write cycles ? 100 year nonvolatile memory data retention ? 24 ? lead soic and 24 ? lead tssop ? write protection for data register ? these devices are pb ? free, halogen free/bfr free and are rohs compliant http://onsemi.com tssop ? 24 y suffix case 948ar pin connections soic ? 24 (w) (top view) nc v cc r l0 r h0 1 r w0 a2 nc nc nc a 0 soic ? 24 w suffix case 751bk see detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. ordering information nc a 3 scl nc nc wp sda a 1 r l1 r h1 cat5419 nc nc r w1 gnd tssop ? 24 (y) (top view) cat5419 wp a 2 r w0 r h0 r l0 v cc nc nc nc nc a 0 nc sda a 1 r l1 r h1 r w1 gnd nc nc nc nc scl a 3 1
cat5419 http://onsemi.com 2 figure 1. functional diagram sda scl a0 a1 a2 a3 nonvolatile data registers wiper control registers control logic 2 ? wire bus interface r w0 r w1 r h0 r h1 r l0 r l1 wp pin descriptions scl: serial clock the cat5419 serial clock input pin is used to clock all data transfers into or out of the device. sda: serial data the cat5419 bidirectional serial data pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wire ? or?d with the other open drain or open collector outputs. a0, a1, a2, a3: device address inputs these inputs set the device address when addressing multiple devices. a total of sixteen devices can be addressed on a single bus. a match in the slave address must be made with the address input in order to initiate communication with the cat5419. r h , r l : resistor end points the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w : wiper the r w pins are equivalent to the wiper terminal of a mechanical potentiometer. wp : write protect input the wp pin when tied low prevents non ? volatile writes to the data registers (change of wiper control register is allowed) and when tied high or left floating normal read/write operations are allowed. see page 8, write protection for more details.
cat5419 http://onsemi.com 3 table 1. pin connections pin soic pin tssop name function 1 19 v cc supply voltage 2 20 r l0 low reference terminal for potentiometer 0 3 21 r h0 high reference terminal for potentiometer 0 4 22 r w0 wiper terminal for potentiometer 0 5 23 a2 device address 6 24 wp write protection 7 1 sda serial data input/output 8 2 a1 device address 9 3 r l1 low reference terminal for potentiometer 1 10 4 r h1 high reference terminal for potentiometer 1 11 5 r w1 wiper terminal for potentiometer 1 12 6 gnd ground 13 7 nc no connect 14 8 nc no connect 15 9 nc no connect 16 10 nc no connect 17 11 scl bus serial clock 18 12 a3 device address 19 13 nc no connect 20 14 a0 device address, lsb 21 15 nc no connect 22 16 nc no connect 23 17 nc no connect 24 18 nc no connect device operation the cat5419 is two resistor arrays integrated with 2wire serial interface logic, four 6 ? bit wiper control registers and sixteen 6 ? bit, non ? volatile memory data registers. each resistor array contains 63 separate resistive elements connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l ). r h and r l are symmetrical and may be interchanged. the tap positions between and at the ends of the series resistors are connected to the output wiper terminals (r w ) by a cmos transistor switch. only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. data can be read or written to the wiper control registers or the non ? volatile memory data registers via the 2 ? wire bus. additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer?s non ? volatile data registers. also, the device can be instructed to operate in an ?increment/decrement? mode.
cat5419 http://onsemi.com 4 table 2. absolute maximum ratings parameters ratings units temperature under bias ? 55 to +125 c storage temperature range ? 65 to +150 c voltage to any pins with respect to v ss (notes 1, 2) ? 2.0 to v cc +2.0 v v cc with respect to gnd ? 2.0 to +7.0 v package power dissipation capability (t a = 25 c) 1.0 w lead soldering temperature (10 s) 300 c wiper current 12 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the minimum dc input voltage is ? 0.5 v. during transitions, inputs may undershoot to ?2.0 v for periods of less than 20 ns. maximum dc voltage on output pins is v cc + 0.5 v, which may overshoot to v cc + 2.0 v for periods of less than 20 ns. 2. latch ? up protection is provided for stresses up to 100 ma on address and data pins from ?1 v to v cc + 1 v. table 3. recommended operating conditions parameters ratings units v cc +2.5 to 6.0 v industrial temperature ? 40 to +85 c table 4. potentiometer characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter test conditions min typ max units r pot potentiometer resistance ( ? 00) 100 k r pot potentiometer resistance ( ? 50) 50 k r pot potentiometer resistance ( ? 10) 10 k r pot potentiometer resistance ( ? 25) 2.5 k potentiometer resistance tolerance 20 % r pot matching 1 % power rating 25 c, each pot 50 mw i w wiper current 6 ma r w wiper resistance i w = 3 ma @ v cc = 3 v 300 r w wiper resistance i w = 3 ma @ v cc = 5 v 80 150 v term voltage on any r h or r l pin v ss = 0 v gnd v cc v v n noise (note 3) tbd nv/ hz resolution 1.6 % absolute linearity (note 4) r w(n)(actual) ? r (n)(expected) (note 7) 1 lsb (note 6) relative linearity (note 5) r w(n+1) ? [r w(n)+lsb ] (note 7) 0.2 lsb (note 6) tc rpot temperature coefficient of r pot (note 3) 300 ppm/ c tc ratio ratiometric temp. coefficient (note 3) 20 ppm/ c c h /c l /c w potentiometer capacitances (note 3) 10/10/25 pf fc frequency response r pot = 50 k (note 3) 0.4 mhz 3. this parameter is tested initially and after a design or process change that affects the parameter. 4. absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 5. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. 6. lsb = r tot / 63 or (r h ? r l ) / 63, single pot 7. n = 0, 1, 2, ..., 63
cat5419 http://onsemi.com 5 table 5. d.c. operating characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter test conditions min max units i cc power supply current f scl = 400 khz 1 ma i sb standby current (v cc = 5 v) v in = gnd or v cc ; sda open 1 a i li input leakage current v in = gnd to v cc 10 a i lo output leakage current v out = gnd to v cc 10 a v il input low voltage ? 1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 1.0 v v ol1 output low voltage (v cc = 3 v) i ol = 3 ma 0.4 v table 6. pin capacitance (note 8) (applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +5.0 v (unless otherwise noted).) symbol test conditions min typ max units conditions c i/o output capacitance (sda) 8 pf v i/o = 0 v c in input capacitance (a0, a1, a2, a3, scl, wp ) 6 pf v in = 0 v table 7. a.c. characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter min typ max units f scl clock frequency 400 khz t i (note 8) noise suppression time constant at scl, sda inputs 50 ns t aa slc low to sda data out and ack out 0.9 s t buf (note 8) time the bus must be free before a new transmission can start 1.2 s t hd:sta start condition hold time 0.6 s t low clock low period 1.2 s t high clock high period 0.6 s t su:sta start condition setup time (for a repeated start condition) 0.6 s t hd:dat data in hold time 0 ns t su:dat data in setup time 100 ns t r (note 8) sda and scl rise time 0.3 s t f (note 8) sda and scl fall time 300 ns t su:sto stop condition setup time 0.6 s t dh data out hold time 50 ns table 8. power up timing (note 8) (over recommended operating conditions unless otherwise stated.) symbol parameter min typ max units t pur power ? up to read operation 1 ms t puw power ? up to write operation 1 ms 8. this parameter is tested initially and after a design or process change that affects the parameter. table 9. write cycles limits (note 9) symbol parameter max units t wr write cycle time 5 ms 9. the write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. d uring the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave add ress.
cat5419 http://onsemi.com 6 table 10. reliability characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter reference test method min typ max units n end (note 10) endurance mil ? std ? 883, test method 1033 1,000,000 cycles/byte t dr (note 10) data retention mil ? std ? 883, test method 1008 100 years v zap (note 10) esd susceptibility mil ? std ? 883, test method 3015 2000 volts i lth (notes 10, 11) latch ? up jedec standard 17 100 ma 10. this parameter is tested initially and after a design or process change that affects the parameter. 11. t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. figure 2. bus timing scl sda in sda out stop condition start condition address ack 8th bit byte n scl sda figure 3. write cycle timing figure 4. start/stop timing start bit sda stop bit scl t wr t su:sta t aa t hd:sta t hd:dat t low t f t dh t low t r t su:dat t high t su:sto t buf
cat5419 http://onsemi.com 7 serial bus protocol the following defines the features of the 2 ? wire bus protocol: 1. data transfer may be initiated only when the bus is not busy. 2. during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock is high will be interpreted as a start or stop condition. the device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the cat5419 will be considered a slave device in all applications. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat5419 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master then sends the address of the particular slave device it is requesting. the four most significant bits of the 8 ? bit slave address are fixed as 0101 for the cat5419 (see figure 5). the next four significant bits (a3, a2, a1, a0) are the device address bits and define which device the master is accessing. up to sixteen devices may be individually addressed by the system. typically, +5 v and ground are hard ? wired to these pins to establish the device?s address. after the master sends a start condition and the slave address byte, the cat5419 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls d own the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat5419 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8 ? bit byte. when the cat5419 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat5419 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. figure 5. acknowledge timing acknowledge 1 start scl from master 89 data output from transmitter data output from receiver
cat5419 http://onsemi.com 8 write operations in the write mode, the master device sends the start condition and the slave address information to the slave device. after the slave generates an acknowledge, the master sends the instruction byte that defines the requested operation of cat5419. the instruction byte consist of a four ? bit opcode followed by two register selection bits and two pot selection bits. after receiving another acknowledge from the slave, the master device transmits the data to be written into the selected register. the cat5419 acknowledges once more and the master generates the stop condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non ? volatile memory. while this internal cycle is in progress, the device will not respond to any request from the master device. acknowledge polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host?s write operation, the cat5419 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address. if the cat5419 is still busy with the write operation, no ack will be returned. if the cat5419 has completed the write operation, an ack will be returned and the host can then proceed with the next instruction operation. write protection the write protection feature allows the user to protect against inadvertent programming of the non ? volatile data registers. if the wp pin is tied to low , the data registers are protected and become read only. similarly, wp pin going low after start will interrupt non ? volatile write to data registers, while wp pin going low after internal write cycle has started will have no effect on any write operation. the cat5419 will accept both slave addresses and instructions, but the data registers are protected from programming by the device?s failure to send an acknowledge after data is received. figure 6. slave address bits * a0, a1, a2 and a3 correspond to pin a0, a1, a2 and a3 of the device. ** a0, a1, a2 and a3 must compare to its corresponding hard wired input pins. a0 a1 a2 a3 1 0 1 0 cat5419 figure 7. write timing s a c k a c k dr1 wcr data s t o p p bus activity: master s t a r t a c k slave/dpp address instruction byte fixed variable op code data register address pot/wcr address sda line
cat5419 http://onsemi.com 9 instructions and register description instructions slave address byte the first byte sent to the cat5419 from the master/ processor is called the slave/dpp address byte. the most significant four bits of the slave address are a device type identifier. these bits for the cat5419 are fixed at 0101[b] (refer to figure 8). the next four bits, a3 ? a0, are the internal slave address and must match the physical device address which is defined by the state of the a3 ? a0 input pins for the cat5419 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the a3 ? a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . instruction byte the next byte sent to the cat5419 contains the instruction and register pointer information. the four most significant bits used provide the instruction opcode i [3:0]. the r1 and r0 bits point to one of the four data registers of each associated potentiometer. the least two significant bits point to one of two wiper control registers. the format is shown in figure 9. table 11. data register selection data register selected r1 r0 dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1 figure 8. identification byte format id3 id2 id1 id0 a3 a2 a1 a0 0101 (msb) (lsb) device type identifier slave address figure 9. instruction byte format i3 i2 i1 i0 r1 r0 0 p0 (msb) (lsb) wcr/pot selection instruction opcode data register selection
cat5419 http://onsemi.com 10 wiper control and data registers wiper control register (wcr) the cat5419 contains two 6 ? bit wiper control registers, one for each potentiometer. the wiper control register output is decoded to select one of 64 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written by the host via write wiper control register instruction; it may be written by transferring the contents of one of four associated data registers via the xfr data register instruction, it can be modified one step at a time by the increment/decrement instruction (see instruction section for more details). finally, it is loaded with the content of its data register zero (dr0) upon power ? up. the wiper control register is a volatile register that loses its contents when the cat5419 is powered ? down. although the register is automatically loaded with the value in dr0 upon power ? up, this may be dif ferent from the value present at power ? down. data registers (dr) each potentiometer has four 6 ? bit non ? volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper control register. any data changes in one of the data registers is a non ? volatile operation and will take a maximum of 5 ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as standard memory locations for system parameters or user preference data. instructions four of the nine instructions are three bytes in length. these instructions are: ? read wiper control register ? read the current wiper position of the selected potentiometer in the wcr ? write wiper control register ? change current wiper position in the wcr of the selected potentiometer ? read data register ? read the contents of the selected data register ? write data register ? write a new value to the selected data register. table 12. instruction set ( note: 1/0 = data is one or zero) instruction instruction set operation i3 i2 i1 i0 r1 r0 0 wcr0/ p0 read wiper control register 1 0 0 1 0 0 0 1/0 read the contents of the wiper control register pointed to by p0 write wiper control register 1 0 1 0 0 0 0 1/0 write new value to the wiper control register pointed to by p0 read data register 1 0 1 1 1/0 1/0 0 1/0 read the contents of the data register pointed to by p0 and r1 ? r0 write data register 1 1 0 0 1/0 1/0 0 1/0 write new value to the data register pointed to by p0 and r1 ? r0 xfr data register to wiper control register 1 1 0 1 1/0 1/0 0 1/0 transfer the contents of the data register pointed to by p0 and r1 ? r0 to its associated wiper control register xfr wiper control register to data register 1 1 1 0 1/0 1/0 0 1/0 transfer the contents of the wiper control register pointed to by p0 to the data register pointed to by r1 ? r0 gang xfr data registers to wiper control registers 0 0 0 1 1/0 1/0 0 0 transfer the contents of the data registers pointed to by r1 ? r0 of both pots to their respective wiper control registers gang xfr wiper control registers to data register 1 0 0 0 1/0 1/0 0 0 transfer the contents of both wiper control registers to their respective data registers pointed to by r1 ? r0 of both four pots increment/decrement wiper control register 0 0 1 0 0 0 0 1/0 enable increment/decrement of the control latch pointed to by p0
cat5419 http://onsemi.com 11 the basic sequence of the three byte instructions is illustrated in figure 11. these three ? byte instructions exchange data between the wcr and one of the data registers. the wcr controls the position of the wiper. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to non ? volatile memory and takes a maximum of t wr to complete. the transfer can occur between one of the potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. four instructions require a two ? byte sequence to complete, as illustrated in figure 10. these instructions transfer data between the host/processor and the cat5419; either between the host and one of the data registers or directly between the host and the wiper control register. these instructions are: ? xfr data register to wiper control register this transfers the contents of one specified data register to the associated wiper control register. ? xfr wiper control register to data register this transfers the contents of the specified wiper control register to the specified associated data register. ? global xfr data register to wiper control register this transfers the contents of all specified data registers to the associated wiper control registers. ? global xfr wiper counter register to data register this transfers the contents of all wiper control registers to the specified associated data registers. increment/decrement command the final command is increment/decrement (figure 6 and 12). the increment/decrement command is different from the other commands. once the command is issued and the cat5419 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each scl clock pulse while sda is low, the selected wiper will move one resistor segment towards the r l terminal. see instructions format for more detail. figure 10. two ? byte instruction sequence s t a r t 0101 a2 a0 a c k i2 i1 i0 r1 r0 a c k sda s t o p id3 id1 id0 p0 device id internal instruction opcode address register address pot/wcr address a1 a3 i3 0 figure 11. three ? byte instruction sequence i3 i2 i1 i0 r1 r0 id3 id2 id1 id0 device id internal instruction opcode address data register address pot/wcr address wcr[7:0] or data register d[7:0] s t a r t 0101 a2 a1 a0 a c k 0p0 a c k sda s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 a3 figure 12. increment/decrement instruction sequence i3 i2 i1 i0 id3 id2 id1 id0 device id internal instruction opcode address data register address pot/wcr address s t a r t 0101 a2 a1 a0 a c k r0 0 p0 a c k sda s t o p i n c 1 i n c 2 i n c n d e c 1 d e c n r1 a3 id2
cat5419 http://onsemi.com 12 figure 13. increment/decrement timing limits scl sda inc/dec command issued voltage out t wrid r w instruction format table 13. read wiper control register (wcr) s t a r t device addresses a c k instruction a c k data a c k s t o p 0 1 0 1 a3 a2 a1 a0 1 0 0 1 0 0 0 p0 7 6 5 4 3 2 1 0 0 0 table 14. write wiper control register (wcr) s t a r t device addresses a c k instruction a c k data a c k s t o p 0 1 0 1 a3 a2 a1 a0 1 0 1 0 0 0 0 p0 7 6 5 4 3 2 1 0 0 0 table 15. read data register (dr) s t a r t device addresses a c k instruction a c k data a c k s t o p 0 1 0 1 a3 a2 a1 a0 1 0 1 1 r1 r0 0 p0 7 6 5 4 3 2 1 0 0 0 table 16. write data register (dr) s t a r t device addresses a c k instruction a c k data a c k s t o p 0 1 0 1 a3 a2 a1 a0 1 1 0 0 r1 r0 0 p0 7 6 5 4 3 2 1 0 0 0
cat5419 http://onsemi.com 13 instruction format (continued) table 17. global transfer data register (dr) to wiper control register (wcr) s t a r t device addresses a c k instruction a c k s t o p 0 1 0 1 a3 a2 a1 a0 0 0 0 1 r1 r0 0 0 table 18. global transfer wiper control register (wcr) to data register (dr) s t a r t device addresses a c k instruction a c k s t o p 0 1 0 1 a3 a2 a1 a0 1 0 0 0 r1 r0 0 0 table 19. transfer wiper control register (wcr) to data register (dr) s t a r t device addresses a c k instruction a c k s t o p 0 1 0 1 a3 a2 a1 a0 1 1 1 0 r1 r0 0 p0 table 20. transfer data register (dr) to wiper control register (wcr) s t a r t device addresses a c k instruction a c k s t o p 0 1 0 1 a3 a2 a1 a0 1 1 0 1 r1 r0 0 p0 table 21. increment (i)/decrement (d) wiper control register (wcr) s t a r t device addresses a c k instruction a c k data s t o p 0 1 0 1 a3 a2 a1 a0 0 0 1 0 0 0 0 p0 i/d i/d . . . i/d i/d note: any write or transfer to the non ? volatile data registers is followed by a high voltage cycle after a stop has been issued.
cat5419 http://onsemi.com 14 package dimensions soic ? 24, 300 mils case 751bk ? 01 issue o e1 e a1 a2 e pin#1 identification b d c a top view side view end view 1 1 h h l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-013. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.31 0.20 0.25 15.20 10.11 7.34 1.27 bsc 2.65 0.30 0.51 0.33 0.75 15.40 10.51 7.60 l 0.40 1.27 2.35 a2 2.05 2.55 1 5o 15o
cat5419 http://onsemi.com 15 package dimensions tssop24, 4.4x7.8 case 948ar ? 01 issue a 1 a1 a2 d top view side view end view e e1 e b l c l1 a symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 7.70 6.25 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.70 7.90 6.55 4.50 notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. 0.60 7.80 6.40 4.40
cat5419 http://onsemi.com 16 example of ordering information (note 14) prefix device # suffix company id cat 5419 w product number 5419 i ? t1 package i = industrial ( ? 40 c to +85 c) temperature range w: soic y: tssop t: tape & reel 1: 1,000 units / reel (soic) 2: 2,000 units / reel (tssop) tape & reel (note 15) (optional) ? 00 resistance ? 25: 2.5 k ? 10: 10 k ? 50: 50 k ? 00: 100 k table 22. ordering information orderable part number resistance (k ) package lead finish cat5419wi ? 25 ? t1 2.5 soic matte ? tin cat5419wi ? 10 ? t1 10 cat5419wi ? 50 ? t1 50 cat5419wi ? 00 ? t1 100 cat5419yi ? 25 ? t2 2.5 tssop cat5419yi ? 10 ? t2 10 cat5419yi ? 50 ? t2 50 cat5419yi ? 00 ? t2 100 cat5419wi25 2.5 soic cat5419wi10 10 cat5419wi50 50 cat5419wi00 100 cat5419yi25 2.5 tssop cat5419yi10 10 cat5419yi50 50 cat5419yi00 100 12. all packages are rohs ? compliant (lead ? free, halogen ? free). 13. the standard lead finish is matte ? tin. 14. the device used in the above example is a cat5419wi ? 00 ? t1 (soic, industrial temperature, 100 k , tape & reel, 1,000/reel). 15. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat5419/d dpp is a trademark of semiconductor components industries, llc. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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